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RFD14N05, RFD14N05SM
Data Sheet February 2004
14A, 50V, 0.100 Ohm, N-Channel Power MOSFETs
These are N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits, gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regulators, switching converters, motor drivers and relay drivers. These transistors can be operated directly from integrated circuits. Formerly developmental type TA09770.
Features
* 14A, 50V * rDS(ON) = 0.100 * Temperature Compensating PSPICE(R) Model * Peak Current vs Pulse Width Curve * UIS Rating Curve * 175oC Operating Temperature * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards"
Ordering Information
PART NUMBER RFD14N05 RFD14N05SM PACKAGE TO-251AA TO-252AA BRAND F14N05 F14N05
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in the tape and reel, i.e., RFD14N05SM9A.
G
S
Packaging
JEDEC TO-251AA
SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE
JEDEC TO-252AA
DRAIN (FLANGE)
(c)2004 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM Rev. C
RFD14N05, RFD14N05SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified RFD14N05, RFD14N05SM 50 50 20 14 Refer to Peak Current Curve Refer to UIS Curve 48 0.32 -55 to 175 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current
TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS IGSS rDS(ON) tON td(ON) tr td(OFF) tf tOFF Qg(TOT) Qg(10) Qg(TH) CISS COSS CRSS RJC RJA VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 40V, ID = 14A, RL = 2.86 Ig(REF) = 0.4mA (Figure 13) TEST CONDITIONS ID = 250A, VGS = 0V (Figure 9) VGS = VDS, ID = 250A VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 150oC VGS = 20V ID = 14A, VGS = 10V, (Figure 11) VDD = 25V, ID 14A, VGS = 10V, RGS = 25, RL = 1.7 (Figure 13) MIN 50 2 TYP 14 26 45 17 570 185 50 MAX 4 25 250 100 0.100 60 100 40 25 1.5 3.125 100 UNITS V V A A nA ns ns ns ns ns ns nC nC nC pF pF pF
oC/W oC/W
Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge Gate Charge at 5V Threshold Gate Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time NOTES: 2. Pulse Test: Pulse Width 300ms, Duty Cycle 2%. 3. Repetitive Rating: Pulse Width limited by max junction temperature. See Transient Thermal Impedance Curve (Figure 3) and Peak Current Capability Curve (Figure 5). SYMBOL VSD trr ISD = 14A ISD = 14A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.5 125 UNITS V ns
(c)2004 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM Rev. C
RFD14N05, RFD14N05SM Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 ID, DRAIN CURRENT (A) 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 175 12 0.8 0.6 0.4 0.2 0
Unless Otherwise Specified
16
8
4
0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
1 THERMAL IMPEDANCE Z JC, NORMALIZED 0.5 0.2 0.1 0.1 0.05 0.02 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 10-3 t, RECTANGULAR PULSE DURATION (s) 100 101 PDM
SINGLE PULSE
0.01 10-5 10-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT CAPABILITY (A)
100
TJ = MAX RATED SINGLE PULSE TC = 25oC
VGS = 20V 100 VGS = 10V
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS:
ID, DRAIN CURRENT (A)
100s 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON)
175 - TC I = I 25 --------------------- 150
1ms
10ms 1 1 DC 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100ms 100
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
(c)2004 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM Rev. C
RFD14N05, RFD14N05SM Typical Performance Curves
50 IAS, AVALANCHE CURRENT (A)
Unless Otherwise Specified (Continued)
35 VGS = 20V 30 ID, DRAIN CURRENT (A) 25 20 15 10 5 0 VGS = 5V VGS = 4.5V 0 2 4 6 VDS, DRAIN TO SOURCE VOLTAGE (V) 8 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 6V VGS = 10V VGS = 8V
TC = 25oC VGS = 7V
STARTING TJ = 25oC 10
STARTING TJ = 150oC If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1] 1 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms) 10
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING FIGURE 7. SATURATION CHARACTERISTICS
IDS(ON), DRAIN TO SOURCE CURRENT (A)
35 30 25 20 15 10 5 0 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V -25oC -55oC 175oC
2.0 ID = 250A
1.5
1.0
0.5
0 -80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
2.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE VGS = VDS, ID = 250A VGS(TH), NORMALIZED GATE 1.5
2.5
2.0
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS= 10V, ID = 14A
THRESHOLD VOLTAGE
1.5
1.0
1.0
0.5
0.5
0 -80
-40
0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC)
200
0 -80
-40
0 40 80 120 TJ, JUNCTION TEMPERATURE (oC)
160
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
(c)2004 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM Rev. C
RFD14N05, RFD14N05SM Typical Performance Curves
700 CISS 600 C, CAPACITANCE (pF) 500 400 COSS 300 200 100 0 0 5 10 15 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 25 CRSS
Unless Otherwise Specified (Continued)
VDS , DRAIN TO SOURCE VOLTAGE (V) 60 VDD = BVDSS 45 VDD = BVDSS 7.5 10
VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD
30 0.75 BVDSS 0.50 BVDSS 0.25 BVDSS RL = 3.57 IG(REF) = 0.4mA VGS = 10V I G ( REF ) I t, TIME (s) G ( REF )
5.0
15
2.5
0
0
20 --------------------I G ( ACT )
80 --------------------I G ( ACT )
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260, FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT CURRENT GATE DRIVE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON VDS VDS VGS RL
+
tOFF td(OFF) tr tf 90%
td(ON)
90%
DUT RGS VGS
-
VDD
0
10% 90%
10%
VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
(c)2004 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM Rev. C
VGS , GATE TO SOURCE VOLTAGE (V)
RFD14N05, RFD14N05SM Test Circuits and Waveforms
(Continued)
VDS RL
VDD
Qg(TOT) VDS VGS = 20V
VGS
+
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) IG(REF) 0 VGS = 10V
DUT IG(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT
FIGURE 19. GATE CHARGE WAVEFORMS
(c)2004 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM Rev. C
RFD14N05, RFD14N05SM PSPICE Electrical Model
.SUBCKT RFD14N05 2 1 3 ;
CA 12 8 8.84e-10 CB 15 14 9.34e-10 CIN 6 8 5.2e-10
10
rev 9/12/94
DPLCAP
5 LDRAIN RSCL1
DRAIN 2
DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 62.87 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.34e-9 LSOURCE 3 7 3.79e-9 MOS1 16 6 8 8 MOSMOD M = 0.99 MOS2 16 21 8 8 MOSMOD M = 0.01
12 GATE 1 LGATE 9 20 RGATE
RSCL2
ESG + EVTO + 18 8 RIN CIN 6 8 VTO 6 + 16
+ 51 5 ESCL 51 50 RDRAIN
DBREAK
11 EBREAK 17 18
+
DBODY
-
21 MOS1
MOS2
-
8
RSOURCE
7
LSOURCE 3 SOURCE
S1A 13 8 S1B CA EGS +
S2A 14 13 S2B 13 CB 6 8 + EDS 5 8 14 IT 15 17 RBREAK 18 RVTO 19 VBAT +
RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 2.2e-3 RGATE 9 20 5.64 RIN 6 8 1e9 RSCL1 5 51 RSCLMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 42.3e-3 RVTO 18 19 RVTOMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
-
-
VBAT 8 19 DC 1 VTO 21 6 0.82 ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/50,6))} .MODEL DBDMOD D (IS = 1.5e-13 RS = 10.9e-3 TRS1 = 2.3e-3 TRS2 = -1.75e-5 CJO = 6.84e-10 TT = 4.2e-8) .MODEL DBKMOD D (RS = 4.15e-1 TRS1 = 3.73e-3 TRS2 = -3.21e-5) .MODEL DPLCAPMOD D (CJO = 26.2e-11 IS = 1e-30 N = 10) .MODEL MOSMOD NMOS (VTO = 3.91 KP = 12.68 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL RBKMOD RES (TC1 = 7.73e-4 TC2 = 2.12e-6) .MODEL RDSMOD RES (TC1 = 5.0e-3 TC2 = 2.53e-5) .MODEL RSCLMOD RES (TC1 = 2.05e-3 TC2 = 1.35e-5) .MODEL RVTOMOD RES (TC1 = -4.44e-3 TC2 = -6.45e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.29 VOFF= -3.29) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.29 VOFF= -5.29) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.25 VOFF= 2.75) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.75 VOFF= -2.25) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global Temperature Options; written by William J. Hepp and C. Frank Wheatley.
(c)2004 Fairchild Semiconductor Corporation
RFD14N05, RFD14N05SM Rev. C
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I8

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